Mentor questa

WILSONVILLE, Ore., June 1, 2010 - Mentor Graphics Corp. (NASDAQ: MENT) today announced the immediate availability of the 0-In® CDC tool version 3.0, the industry's most complete and effective solution for clock domain crossing verification. The patented technology in the 0-In CDC tool enables comprehensive analysis and verification of clock domains, synchronization, protocols, and reconvergence, using a combination of static formal verification and simulation in a highly-automated flow. As a result, the 0-In CDC tool enables verification of the most complex designs, with little user effort. The 0-In CDC v3.0 tool supports SystemVerilog, Verilog, and VHDL with a wide variety of design styles and synchronization methods. In version 3.0, the 0-In CDC tool supports top-down, bottom-up, and mixed approaches for hierarchical analysis, and gives the user more control over the verification process. The 0-In CDC v3.0 tool includes patented technology that enables verification of the effects of metastability and reconvergence during simulation. In addition, the 0-In CDC v3.0 tool exports data to Mentor’s Unified Coverage Data Base (UCDB). Together, these enhancements enable users to verify larger and more complex designs and integrate the results into a complete coverage-driven verification flow. “Clock-domain crossing verification is an increasingly-difficult challenge in today's designs, which have large numbers of typically asynchronous clock domains. It is a complex verification problem that requires a multi-faceted solution,” said John Lenyo, general manager, Design Verification Technology (DVT) division. “The 0-In CDC tool provides such a solution by combining our best-in-class formal technology with the industry-leading Questa® verification platform to attack the problem from several directions. Version 3.0 builds on extensive customer experience over the past 5 years to provide even greater flexibility and power.” Questa Functional Verification Platform The Questa functional verification platform combines high performance and high capacity with the most comprehensive verification capabilities in the industry. Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVCs), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB). Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM) that delivers unrivaled language and feature support in any design and verification flow. About Mentor Graphics Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located

WILSONVILLE, Ore., October 17, 2012—Mentor Graphics Corp. (NASDAQ: MENT) today announced new formal-based technologies in the Questa® Verification Platform that provide mainstream users with the ability to more easily perform exhaustive formal verification analysis. The new Questa AutoCheck technology delivers fully automated formal checking analysis, while the Questa CoverCheck tool provides 100% code coverage closure. The Questa Verification Platform now also offers expanded clock-domain crossing (CDC) capabilities. Formal verification offers exhaustive functional analysis of all possible design behaviors without the need to specify the test stimulus, enabling verification early in the design cycle, before creation of a simulation testbench. However, in the past, the promise of formal verification was only realized by verification teams with formal analysis experts that had to expend a high amount of effort to achieve results. The Questa platform changes all that by delivering a wide spectrum of formal applications that range from fully automatic formal checking with AutoCheck, a powerful, push-button technology that everyone can easily use, to property checking with custom coded assertions for advanced users. The Questa platform now offers a broad arsenal of verification solutions that seamlessly blend simulation and formal-based technologies with common compilation and user interface features as well as the Unified Coverage Database (UCDB). Questa CoverCheck Enables 100% Code Coverage Closure The Questa CoverCheck technology accelerates the process of code coverage closure. Code coverage closure typically involves many engineering weeks of effort to manually review code coverage holes to determine if they can be safely ignored and if not, to generate hand- crafted simulation tests to cover them. Questa CoverCheck makes it easy for non-expert users to leverage formal methods to complete this process by automatically identifying the set of reachable and unreachable coverage bins. Consequently, it significantly reduces the time required for code coverage sign-off, bringing predictability to the schedule. CoverCheck also ensures higher design quality by preventing bugs from slipping through the verification process due to mistakenly ignored code coverage bins. Questa Formal with AutoCheck for Mainstream Users AutoCheck analyzes RTL designs and automatically synthesizes assertions that are then processed by powerful formal engines to check for

Plugin or text based industry standard formats like SystemRDL, RALF, IP-XACT. IDesignSpec generator takes the specifications and builds the synthesizable RTL code, SV-UVM model, C/C++ headers and the documentation in HTML, Word, and PDF formats.The specification captures the hierarchical structure of the designs, and let users define registers, register blocks, references to the register blocks or even references to the other register specification files. Any change required in the functionality can be included in the specs and modified output can be generated. IDesignSpec also offers the assistance to the verification team by generating the verification environment for the registers & memory banks and their interface to the AMBA buses.ARV™ is an add-on product to IDesignSpec that expands an already powerful register specification solution with capability to automate the register specification-creation-verification process for ARM-based SoCs, IP and FPGA semiconductor projects. ARV saves semiconductor teams time and improves quality by enabling complete code coverage for design registers that are the key integration point for semiconductor design, IP, software and interfaces. ARV-Formal uses formal tools such as Mentor Questa® Formal and OneSpin’s DV-Verify 360™ to ensure that Register operations conform to the user specification and ARM standards. ARV-Sim can use Mentor Graphics’ Questa® VIP to create a UVM based simulation environment to verify the registers automatically.About AgnisysAgnisys provides IDesignSpec for specification driven system development for ARM-based designs. Client IP for AMBA buses such as AXI, APB, AHB AXI4LITE, AHB3LITE can be generated using IDesignSpec. Along with synthesizable IP code, a verification test environment,

Correct sequential design behavior. Using AutoCheck, designs are easily verified to be free from common functional errors without the need to write a testbench or assertions. In addition, performance improvements based on breakthrough formal engines and formal model optimizations deliver improved quality of results and a significant decrease in compute resource consumption. This release also delivers Questa Formal Multi-Core, a new capability that enables multi-core and multi- computer distribution of formal jobs, further improving the throughput of formal analysis and optimizing the use of compute farm resources.“One of the challenges to achieving a high degree of verification quality is the wide spectrum of functional problems that must be accounted for, ranging from common RTL coding errors to obscure corner case bugs,” said Dr. Byeong E. Min, master of System LSI infrastructure design center, Device Solutions, Samsung Electronics. “We are pleased with the enhanced verification productivity and design quality that we have achieved by deploying formal-based technologies in the Questa platform, which address some of these problem areas that are not well covered by traditional methods.” Questa CDC for High Performance Analysis and Unlimited Design Sizes Questa CDC is used extensively by leading semiconductor design teams and it sets the bar for capacity, ease of use and quality of results. This release delivers additional performance gains, boosting the capacity of Questa CDC to match the complexity of today’s SoC designs. Questa CDC also supports unlimited design sizes through hierarchical CDC analysis. It automatically generates highly accurate, block-level CDC interface logic models that enable chip-level CDC verification with full debug visibility. “On an industry-wide basis, we are seeing increased demand for high-performance, easy-to- use formal methods in order to reduce the overall time to verification in terms of human and technical resources,” said John Lenyo, vice president and general manager of the Design Verification Technology division of Mentor Graphics. “The new formal-based capabilities of the Questa platform make it very attractive in terms of both state-of-the-art performance and capacity advances, as well as practical in terms of automation, to incorporate the power of formal technology into existing verification flows.” Product Availability and

Simulating the circuit’s behavior at different frequencies to observe the frequency response of the system.Simulation Testing Tools.There are several simulation testing tools available, such as:SPICE-based simulators (e.g., LTspice, PSpice, etc.)Digital logic simulators (e.g., ModelSim, XSIM, etc.)Mixed-signal simulators (e.g., Cadence Virtuoso, Mentor Graphics Questa, etc.) Additional Verification and Testing Techniques Peer ReviewHaving a colleague or a fellow engineer review the schematic symbols and the PCB design can help identify errors or discrepancies that may have been overlooked.Design Rule Check (DRC)Running a DRC using your EDA tool can help identify issues such as incorrect symbol-to-footprint mapping, missing or duplicate connections, and other rule violations.Electrical Rule Check (ERC)Performing an ERC can help identify electrical issues, such as unconnected pins, short circuits, or incorrect power supply connections.Verifying and testing PCB symbols is a crucial step in the PCB design process. By utilizing symbolic logic verification, simulation testing, and other verification techniques, you can ensure the accuracy and reliability of your PCB design, minimizing the risk of errors and reducing the need for costly rework. PCB symbols are a vital part of the electronic design process, and their use is essential for creating clear and concise documentation. By using standardized symbols, engineers and technicians can communicate their designs effectively and ensure that everyone involved in the process understands the intended functionality.At JHDPCB we are a high-tech enterprise that has been manufacturing a full range of PCBs since 2009. With more than 10 years of experience in the industry, we are specialized in the R&D, production,

Use HyperLynx to identify, analyze and solve design problems for optimum results. View Details Questa Core/Visualizer Advanced Topics Extend your knowledge of Advanced Questa Simulator features and efficiently analyze and debug HDL code. View Details Questa Core: HDL Simulation Training Learn to use Advanced Questa Simulator GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations. View Details Questa Formal Verification On-Demand Training Course You will learn how to set up your design in Questa Formal software and how to use AutoCheck, XCheck, CoverCheck and PropCheck to debug and verify your design. View Details Questa Lint On-Demand Training Course Learn how to use Questa® Lint to perform a fast check of your HDL RTL, looking for completeness and consistency issues. View Details Questa SIM SystemC On-Demand Training Course In this self-paced course, you will receive an overview of SystemC and learn how to simulate SystemC designs in Questa. View Details Questa Verification IP On-Demand Training Course Learn how to create stimulus and check results for standard protocols with Questa Verification IP. Build a UVM testbench or add QVIP to an existing one. View Details ReqTracer for FPGA/ASIC Design Assurance On-Demand Training Course Learn how to use ReqTracer to automate tracing of design requirements to design and test data associated with an FPGA/ASIC design by watching live recordings. View Details RF Design in Xpedition Flow Learn at your own pace using this course, to efficiently implement RF and mixed technology RF designs on an Xpedition PCB Design. View Details Schematic Entry in the Xpedition Flow Learn at your own pace using this course, how to use Xpedition Designer to create schematic, select parts using DataBook and prepare for layout. View Details Schematic Entry in the Xpedition Flow (Modern UX) New Gain proficiency in project management, schematic capture, part selection using xDX DataBook, and prepare schematic for layout using Xpedition Designer. View Details Schematic Entry in the Xpedition Flow with EDM New Gain proficiency in project management, schematic capture, part selection using DataBook, and prepare schematic for layout using Xpedition Designer.